Quartus II Software: Timing Analysis
17 Jan 2018

Quartus II Software: Timing Analysis

You will learn how to constrain & analyze a design for timing using the TimeQuest timing analyzer in the Quartus II software. This includes understanding FPGA timing parameters, writing Synopsys Design Constraint (SDC) files, generating various timing reports in the TimeQuest timing analyzer & applying this knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets timing, you will see how the TimeQuest timing analyzer makes it easy to create timing constraints to help you meet those requirements.

At Course Completion you will be able to:

  •  Understand the TimeQuest timing analyzer timing analysis design flow
  •  Apply basic and complex timing constraints to an FPGA design
  •  Analyze an FPGA design for timing using the TimeQuest timing analyzer
  •  Write and manipulate SDC files for analysis and controlling the Quartus II compilation

Prerequisites 

We recommend completing the following courses:

  • Quartus II Software: Foundation
  •  The Quartus II Software: Foundation (Online Training)

Skills Required 

  •  Experience with PCs and the Windows operating system
  •  Completion of "Quartus II Software: Foundation" online or instructor-led course OR a working knowledge of the Quartus II software

Follow-on Courses 

Upon completing this course, we recommend the following courses (in no particular order):

  •  Quartus II Software: Foundation
  •  Quartus II Software: Debug & Analysis
  •  Advanced Timing Analysis with TimeQuest
  •  Timing Closure with the Quartus II Software

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