13 Feb 2018 t/m 12 Feb 2018
You will learn & practice efficient coding techniques for writing synthesizable VHDL for programmable logic devices (FPGAs & CPLDs). While the concepts presented will mainly target Altera® FPGA devices using the Quartus® II software, many can be applied to other devices & synthesis tools. You will gain experience writing behavioral & structural code & learn to effectively code common logic functions including registers, memory, & arithmetic functions. You will use VHDL constructs to parameterize your designs to increase their flexibility & reusability. You will also be introduced to testbenches, VHDL constructs used to build them, & common ways to write them. The exercises will use the Quartus II software version to process VHDL code & ModelSim®-Altera software for simulation.
At Course Completion you will be able to:
- Develop coding styles for efficient synthesis when:
- Targeting device features.
- Inferring logic functions.
- Using arithmetic operators.
- Writing state machines.
- Use Quartus II software RTL Viewer to verify correct synthesis results.
- Incorporate Altera structural blocks in VHDL designs.
- Write simple testbenches for verification.
- Create parameterized designs.
We recommend completing the following courses:
- Completion of the "Introduction to VHDL" course or some prior knowledge and use of VHDL.
- Background in digital logic design.
- Understanding of synthesis and simulation processes.