22 May 2019
Intel® Quartus® Prime Software: Timing Analysis with Timing Analyzer
You will learn how to constrain & analyze a design for timing using the timing analyzer in the Intel® Quartus® Prime software. This includes understanding FPGA timing parameters, writing Synopsys* Design Constraint (SDC) files, generating various timing reports in the timing analyzer & applying this knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets timing, you will see how the timing analyzer makes it easy to create timing constraints to help you meet those requirements.
At Course Completion you will be able to:
- Understand the timing analyzer timing analysis design flow.
- Apply basic and complex timing constraints to an FPGA design
- Analyze an FPGA design for timing using the timing analyzer
- Write and manipulate SDC files for analysis and controlling the Intel® Quartus® Prime compilation.
- Experience with PCs and the Windows operating system.
- Completion of "The Intel® Quartus® Prime Software: Foundation" online or instructor-led course OR a working knowledge of the Intel® Quartus® Prime software.
We recommend completing the following courses:
- The Intel® Quartus® Prime Software: Foundation.
- The Intel® Quartus® Prime Software: Foundation (Standard Edition) (Online Training)
Upon completing this course, we recommend the following courses (in no particular order):
- Advanced Timing Analysis with TimeQuest