15 nov 2016
Release of IO Checker 3.3
we are pleased to announce the release of IO Checker 3.3.
It is the best tool around to verify if your FPGA is correctly connected on a PCB.
Within half an hour you can compare user IO, power and ground between the FPGA and the schematic netlist and easily concentrate on (potential) mismatches.
Highlights in this new release are:
- A schematic capture interface to Altium Designer and Cadence Allegro.
- New devices from Altera and Xilinx.
- Power extraction for Xilinx Vivado.
- Cadence Allegro 'chipfile.prt' editor to simplify pin-swapping.
More information about this new release can be found on the HDL Works website on the Whats New page.
More information on IO checker can be found on the HDL Works website at the IO Checker product page.